Varian Data Machines

DATA/620

The first DCI DATA/620 was installed in 1965 and could be rented for $ 900 per month, a lower cost than most other computers then available.^[5] The DATA/620 was a parallel, binary 16-bit general-purpose digital computer with magnetic-core memory expandable to 32,768 words. An 18-bit word length (for data, not addresses or instructions) was optionally available. A basic machine cycle took 1.8 microseconds, and the core memory read time was 700 nanoseconds. The computers use two's complement arithmetic and had four main registers - accumulator A, accumulator extension B, an index register X and a program counter register. Some variants supported microprogramming. These models used a hardware front panel console that allowed starting and stopping the machine, examining memory and registers and changing memory or registers with front-panel switches. The company proudly proclaimed that most debugging was now possible "without even having to use an oscilloscope".^[6]: 10 The DATA/620 was built with discrete transistors in a bit-sliced architecture (that is, the arithmetic unit and all registers for one bit are contained in two circuit boards).^[6]: 18 The system of circiut boards was called "VersaLOGIC", with logic levels of 0 V and -12 V.^[6]: 25 Architecture and instruction set of the DATA/620 were similar to other minicomputers of the era, such as the Honeywell 316 or the PDP-8. Features typical of early minicomputers (and not found in later microprocessor architectures) include:

• The absence of a stack pointer. Instead, the return address of a subroutine call is stored in the first word of the subroutine (see PDP-8 § Subroutines for a more detailed discussion).
• The possibility to "micro-code" several operations in one instruction word (e.g. set A, B, and X to zero in one operation; see PDP-8 § OPR (OPeRate) for comparison). Likewise, a single jump instruction can test several condition at once, i.e. the jump is performed if all the tested conditions are true (e.g. A, B, and X are all zero).
• Multi-level indirect addressing. Instead of the address of an operand, an instruction contains the address of the address of the operand.

Register A serves as the primary accumulator, that is, it supplies one operand for arithmetic and logic operations and receives the result of the operation. The second operand for these operations is read from memory. The first 2048 words of memory can be addressed directly by arithmetic and logic operations. Addressing the full memory range requires the use of registers B or X as an index register or the use of an indirect address in the first 512 words of memory. The second operand could also be addressed relative to the program counter P (up to 512 words) or be an immediate, 16-bit value. A hardware option could be purchased that added multiplication and division instructions (which combined A and B as a 32-bit register).

A DATA/620 with up to 8192 Words or memory weighed 400 lb (180 kg) and consumed 500 W.^[6]: 25

DATA 620/i

The 620/i^[6]: 1 shipped in June 1967;^[7] it and subsequent series were made with integrated circuit transistor–transistor logic from the 7400 series. The system was packaged in a 19-inch rack and consumed 340 watts at 120 V AC. The 620/F was a variation with a faster machine cycle time of 750 nanoseconds.

The ruggedized R-620/i was announced in 1968.^[8]

A lower cost 520/i shipped in October 1968^[7]

Varian 620/L

The 620/L-100 was released in 1973. It had a cycle time of 950 nanoseconds and a more compact system chassis than the 620/F.^[9] The Sperry V70 series had semiconductor memory, but could also support magnetic core. Various models were released between 1972 and 1977.^[10]